Appendix O

1. Access to disc routines in boot ROM provided.
2. CPU registers are saved in low memory prior to memory test. Low memory from 0 to 0ffh is not tested or cleared.

The boot ROM loads diskette resident systems from a description contained on track 0 sector 0 of a diskette. A logical flow follows:

1. Disable interrupts
2. Clear the CRT controller.
3. If a memory test of the first 16K of memory fails then halt the boot. Else set the first 16K of memory to zero.
4. If a test of the screen RAM fails then halt the boot. Else set the screen RAM to zero.
5. Load the character set into the dot matrix.
6. Initialise, clear and set to high intensity the CRT.
7. Turn on the arrow display.
8. Initialise the diskette and display the diskette image at middle screen.
9. Turn off all disc drives.
10. Select drive A.
11. If a drive door closes, select that drive as the boot disc otherwise every 32nd time blink the arrow display.
12. When a drive has been selected then turn off the display and turn on the disc drive motor.
13. Read a header record from track 0 sector 0 and if an error go to the disc error output.
14. Otherwise display the clock and memory determination icons and test for end of memory.
15. Save the memory size for comparison with system requirements and display it on the CRT with the clock off.
16. Turn the clock on and read the diskette definitions and if a disc read error occurs report it via the disc display.
17. Check the disc label and if invalid go to the not a system disc error display.
18. Bring the disc online with all disc parameters loaded.
19. Compute the parameters to load the system and then load the system into memory. After successfully loading it transfers to the system via a programmed interrupt 255.
20. On the event of a reportable error display it then waits for the disc door to open at which time control is passed to 6. above.

At power on in the middle of the bottom line a flashing arrow and a diskette are displayed if both disc drive doors are open. When a drive door is detected to have closed that disc is selected for loading a system. A memory symbol, a large 'M' at the left of middle is displayed and a clock image replaces the arrow/disc formerly displayed. If the memory required cannot be read from the disc record then an image containing, diskette, large 'X', and an error code is displayed on right of middle. If the memory required by the target system is more than the processors capacity then an image with a large 'X' and the size of memory in paragraphs follows the 'M' at left of middle.

New boot EPROMs have been developed which allow the Sirus 1 to boot off any available device; ie. floppy, hard disc, network, etc. These EPROMs not only eliminate the need for specialised sets which were used in the past, but also provide some primitive yet effective diagnostic capabilities to field service personnel.

A system equipped with Universal EPROMs can be easily identified by the different ICONS which are displayed following a power on reset or push button reset. The memory sizing ICON is reported in kilo-bytes rather than Segments (M 128K instead of M 2000). The type of device ICON from which the CPU is trying to boot from is displayed along with the specific number (0 for floppy A or hard disc 0, and 1 for floppy B or hard disc 1). A new ICON has been installed and will be presented to the screen while the system tries to boot off the Network.

In the case where there is enough functional circuitry to report the error to the screen, the error code will be reported on the 25th line along with ICON display. The method for more catastrophic errors is to report, via the output instruction, the type of error in the UPPER NIBBLE of the data byte, and if possible the failing device in the LOWER NIBBLE of the data byte. This is done by doing a write to I/O port 0FFFF hex. The boot code then loops on this instruction allowing a technician to use an oscilloscope to analyse the failure.

Two examples of CPU error detection where there is sufficient circuitry available to report failure to the screen, are listed below.

In this example, the CPU has found the first 16K bytes of dynamic ram to be functional but found a faulty ram location in an area above the 16K bytes. The code 3X hex is defined as follows; the upper nibble 3 indicates a single bit failure in dynamic ram, and the X would be in the range of 0 - F to indicate which ram bit contained the failure.

This error code is defined as follows; the upper nibble 4 indicates a multiple bit dynamic ram failure, and the lower nibble X indicates the first failing ram bit (starting with the most significant bit). Replace this device and repeat test until system boots or other error code is present. As stated previously the Universal Boot EPROM also tests the PIC and the three 6522's resident on the CPU board. The CPU will write to some of the registers within the devices and then attempt to read back the value written to that register. If the CPU cannot read back the same value written, then the faulty I/O device will be reported to the 25th line on the CRT screen. This error code will appear to the right of the Device ICON, and is described below.